This invention relates to semiconductor devices, and more particularly to CMOS delay circuits of the type used for internal time-out functions in clock generators for VLSI semiconductor dynamic memory devices, or the like.
Semiconductor dynamic memory devices of the N-channel type of the type shown, for example, in U.S. Pat. No. 4,239,993, issued to McAlexander, White and Rao, assigned to Texas Instruments, employ a large number of internal clocks which are generated using delay circuits such as that as illustrated in U.S. Pat. No. 4,239,990, issued to Hong and Redwine, assigned to Texas Instruments, or in pending application Ser. No. 419,118, filed Sept. 16, 1982 by Reddy, and now U.S. Pat. No. 4,521,701, also assigned to Texas Instruments. When manufacturing dynamic memory devices using CMOS processing, however, the delay stages must be of course redesigned to minimize the power dissipation commensurate with the low-power characteristics of the remainder of the CMOS circuitry.
It is the principal object of this invention to provide improved CMOS delay circuits for semiconductor integrated circuits such as dynamic memory devices. Another object is to provide time-out circuits which are compensated for variations in the supply voltage, and for threshold voltage changes due to processing and temperature variations.